1. Field of the Invention
The present invention relates to a thin film transistor, and more particularly, to a method of manufacturing a thin film transistor for use in a liquid crystal display (LCD) device.
2. Discussion of the Related Art
Of known liquid crystal display devices, an active matrix liquid crystal display (AM-LCD) device, in which the thin film transistors and the pixel electrodes are arranged in the form of a matrix, has recently received a great deal of attention because of its high resolution and good performance for displaying the moving images.
FIG. 1 is a cross sectional view illustrating a typical AM-LCD device. As shown in FIG. 1, the LCD device 20 includes lower and upper substrates 1 and 3, with a liquid crystal layer 10 interposed between the upper and lower substrates. The lower substrate 1 has a thin film transistor “S” (TFT) as a switching element and a pixel electrode 14. The upper substrate 3 has a color filter 8 and a common electrode 12. The pixel electrode 14 is formed over a pixel region “P” and serves to apply a voltage to the liquid crystal layer 10 along with the common electrode 12, and the color filter 8 serves to implement natural colors. A sealant 6 seals edges of the lower and upper substrates 1 and 3 to prevent a leakage of the liquid crystal.
A TFT for use in the LCD device is usually an inverted staggered-type TFT because its structure is simple and its performance is excellent. The inverted staggered-type TFT is divided into a back channel etch type TFT and an etch-stopper type TFT. The present invention is explained with a particular focus on the back channel etch type TFT, whose manufacturing process is relatively simple.
FIGS. 2A to 2E are cross sectional views illustrating a process for manufacturing an array substrate for use in a conventional LCD device. First, as shown in FIG. 2A, a gate electrode 30 is formed on a substrate 1. The gate electrode 30 is made of a low resistive material such as aluminum in order to prevent a signal delay.
Then, as shown in FIG. 2B, a gate insulating layer 32, an amorphous silicon layer 34, and a doped amorphous silicon layer 36 are sequentially deposited over the whole substrate 1. The amorphous silicon layer 34 and the doped amorphous silicon layer 36 are patterned into an active layer 35. The gate insulating layer 32 includes SiNx or SiO2 that can be deposited at the low temperature (for example, of less than 350° C.) and has a good insulation property.
The doped amorphous silicon layer 36 is formed by ion-doping gas containing one of the Group III or one of the Group V elements (for example, boron or phosphorous) after the amorphous silicon layer is deposited. For example, an n+ amorphous silicon layer (n+ a-Si:H) formed by ion-doping the phospine gas PH3 containing the phosphorous (P) is usually used as the doped amorphous silicon layer 36.
Subsequently, as shown in FIG. 2C, source and drain electrodes 38 and 40 are formed on the doped amorphous silicon layer 36. The source and drain electrodes 38 and 40 are spaced apart from each other and overlap both end portions of the gate electrode 30. Thereafter, using the source and drain electrodes 38 and 40 as a mask, a portion of the doped amorphous silicon layer 36 between the source and drain electrodes 38 and 40 is etched to form a channel region “Ch”.
Next, as shown in FIG. 2D, a passivation layer 42 is formed over the whole substrate 1. The passivation layer 42 serves to protect the channel region “Ch” from humidity, external impact and the like, and is preferably made of an inorganic material such SiNx or an organic material such as benzocyclobutene (BCB). The passivation layer 42 includes a contact hole 44 on a portion of the drain electrode 40.
Finally, as shown in FIG. 2E, a pixel electrode 46 is formed on the passivation layer 42 and is electrically connected with the drain electrode 40 through the contact hole 44. Preferably, the pixel electrode 46 is made of indium tin oxide (ITO). Therefore, most of the important components are arranged on the array substrate.
The characteristics of the lower array substrate usually depend on materials used for the respective components. For example, in case of the large-sized liquid crystal display device of more than 18 inches having a high resolution such as SXGA and UXGA, the resistivity of the material used for the gate and data lines becomes the important parameter for determining the display quality. For example, a display distortion may occur because of cross-talk by the signal delay due to the line resistance of the gate electrode. Therefore, conventional LCD devices have employed aluminum or aluminum alloy for metal lines such as the gate and data lines. However, aluminum has poor corrosion resistance and may cause a line defect due to a hillock or bump that may be generated during subsequent high temperature process. Moreover, increasing thickness or width of the metal line in order to reduce the line resistance may lead to a decrease in aperture ratio and occurrence of step portion (coverage).
In other words, as shown in FIG. 3, when the gate electrode 30 is thickly formed to reduce its resistance, the gate insulating layer 32, the amorphous silicon layer 34, the doped amorphous silicon layer 36, and the drain electrode 40 may have a line open because the step difference becomes large and their step coverage is thus insufficient. Besides, because of the step difference of the gate electrode 30, a parasitic capacitance “Cpc” occurs between the gate electrode 30 and the drain electrode 40 and, therefore a flicker develops significantly, thereby causing display distortion.
For the foregoing reasons, there is a need for a thin film transistor having an improved display quality as well as a high aperture ratio.